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HN58X24256AS two-wire serial interface 256k eeprom (32-kword 8-bit) rej03c0316-0001 preliminary rev.0.01 mar.22.2007 description hn58x24xxx series are two-wire se rial interface eeprom (electrical ly erasable and programmable r o m ) . they real i ze hi gh speed, l o w power consumpt i on and a hi gh l e vel of rel i abi l i t y by empl oyi ng advanced m nos memory t echnol ogy and c m os process and l o w vol t a ge ci rcui t r y t echnol ogy. they al so have a 64-byt e page programmi ng funct i on to mak e th eir w r ite o p e ratio n faster. not e : r e nesas technol ogy?s seri al eepr o m are aut hori zed for usi ng consumer appl i cat i ons such as cel l u l a r phone, camcorders, audi o equi pment . therefore, pl ease cont act r e nesas technol ogy?s sal e s offi ce before usi ng i ndust r i a l appl i cat i ons su ch as aut o mot i ve syst ems, embedded cont rol l ers, and met e rs. features ? si ngl e suppl y: 1.8 v t o 5.5 v ? two-wire serial interface (i 2 c serial bus) ? c l ock frequency: 400 khz ? power di ssi pat i on: ? st andby: 3 a (max) ? active (read): 1 ma (max) ? active (write): 5 ma (max) ? aut o mat i c page wri t e : 64-byt e/ page ? write cycle time: 5 ms ? endurance: 10 6 cycles ? dat a ret e nt i on: 10 years prel i m i n ary: the speci fi cat i ons of t h i s devi ce are subj ect t o change wi t hout not i ce. pl ease cont act your nearest r e nesas technol ogy?s sal e s dept . regardi ng speci fi cat i ons. rev.0.01, mar.22. 2007, page 1 of 20
HN58X24256AS ? smal l si ze packages: sop-8pi n, tssop-14pi n ? shi ppi ng t a pe and reel ? tssop 14-pi n: 2,000 ic / r eel ? sop 8-pi n: 2,500 ic / r eel ? temperature range: ? 40 t o +85 c ? lead free product s . ordering information type no. internal organization operating voltage f requency package HN58X24256ASfpi 256k bit (32768 8-bit) 1.8 v to 5.5 v 400 khz 150 mil 8-pin plastic sop prsp0008df-b (fp-8dbv) lead free HN58X24256ASti 256k bit (32768 8-bit) 1.8 v to 5.5 v 400 khz 14-pin plastic tssop ptsp0014ja-c (ttp-14dbv) lead free pin arrangement 1 2 3 4 5 6 7 14 13 12 11 10 9 8 a0 a1 nc nc v cc wp nc nc nc a2 v ss nc scl sda (top view) 14-pin tssop 1 2 3 4 8 7 6 5 a0 a1 a2 v ss v cc wp scl sda (top view) 8-pin sop rev.0.01, mar.22. 2007, page 2 of 20
HN58X24256AS pin description pin name function a0 to a2 device address scl serial clock input sda serial data input/output w p w r i t e p r o t e c t v cc p o w e r s u p p l y v ss g r o u n d n c n o c o n n e c t i o n control logic high voltage generator address generator x decoder y decoder memory array y-select & sense amp. serial-parallel converter v cc v ss wp a0, a1, a2 scl sda block diagram absolute maximum ratings p a r a m e t e r s y m b o l v a l u e u n i t supply voltage relative to v ss v cc ? 0.6 to +7.0 v input voltage relative to v ss v i n ? 0.5 * 2 to +7.0 * 3 v operating temperature range * 1 t o p r ? 40 to + 85 c storage temperature range tstg ? 65 to + 125 c notes: 1. including electrical c haracteristics and data retention. 2. vin (min): ? 3.0 v for pulse width 50 ns. 3. should not exceed v cc + 1.0 v. rev.0.01, mar.22. 2007, page 3 of 20
HN58X24256AS dc operating conditions p a r a m e t e r s y m b o l m i n t y p m a x u n i t supply voltage v cc 1 . 8 ? 5 . 5 v v ss 0 0 0 v input high voltage v ih v cc 0.7 ? v cc + 0.5 v input low voltage v il ? 0.3 * 1 ? v cc 0.3 v operating tem p e r a t u r e t o p r ? 40 ? + 8 5 c notes: 1. v il (min): ? 1.0 v for pulse width 50 ns. dc characteristics (ta = ? 40 t o +85 c, v cc = 1.8 v t o 5.5 v) p a r a m e t e r s y m b o l m i n t y p m a x u n i t t e s t c o n d i t i o n s input leakage current i li ? ? 2 . 0 a v cc = 5.5 v, vin = 0 to 5.5 v output leakage current i lo ? ? 2 . 0 a v cc = 5.5 v, vout = 0 to 5.5 v standby v cc current i sb ? 1 . 0 3 . 0 a vin = v ss or v cc read v cc current i cc1 ? ? 1 . 0 m a v cc = 5.5 v, read at 400 khz write v cc current i cc2 ? ? 5 . 0 m a v cc = 5.5 v, w r ite at 400 khz output low voltage v ol 2 ? ? 0 . 4 v v cc = 2.7 to 5.5 v, i ol = 3.0 ma v ol 1 ? ? 0 . 2 v v cc = 1.8 to 2.7 v, i ol = 1.5 ma capacitance (ta = +25 c, f = 1 mhz) parameter symbol min typ max unit test conditions input capacitance (a0 to a2, scl, w p ) cin * 1 ? ? 6.0 pf vin = 0 v output capacitance (sda) c i/o * 1 ? ? 6.0 pf vout = 0 v note: 1. this parameter is sampled and not 100 % tested. rev.0.01, mar.22. 2007, page 4 of 20
HN58X24256AS ac characteristics (ta = ? 40 t o +85 c, v cc = 1.8 t o 5.5 v) test conditions ? input pul es l e vel s : ? v il = 0.2 v cc ? v ih = 0.8 v cc ? input ri se and fal l t i me: 20 ns ? input and out put t i m i ng reference l e vel s : 0.5 v cc ? output load: ttl gate + 100 pf p a r a m e t e r s y m b o l m i n t y p m a x u n i t n o t e s clock frequency f scl ? ? 4 0 0 k h z clock pulse width low t lo w 1 2 0 0 ? ? n s clock pulse width high t high 6 0 0 ? ? n s noise suppression time t i ? ? 5 0 n s 1 access time t aa 1 0 0 ? 9 0 0 n s bus free time for next mode t buf 1 2 0 0 ? ? n s start hold time t hd.sta 6 0 0 ? ? n s start setup time t su.sta 6 0 0 ? ? n s data in hold time t hd.dat 0 ? ? n s data in setup time t su.dat 1 0 0 ? ? n s input rise time t r ? ? 3 0 0 n s 1 input fall time t f ? ? 3 0 0 n s 1 stop setup time t su.sto 6 0 0 ? ? n s data out hold time t dh 5 0 ? ? n s w r ite protect hold time t hd.wp 1 2 0 0 ? ? n s w r ite protect setup time t su.wp 0 ? ? n s write cycle time t wc ? ? 5 m s 2 erase/w r ite endurance ? ? 1 0 6 ? c y c l e s 3 notes: 1. this parameter is sampled and not 100 % tested. 2. t wc is the time from a stop condition to t he end of internally controlled write cycle. 3. this parameter is samp led and not 100% tested (ta = 25 c). rev.0.01, mar.22. 2007, page 5 of 20
HN58X24256AS timing waveforms bus timing t f 1/f scl t high t su .st a t hd .st a t hd .d a t t su .d a t t su .st o t bu f t dh t aa t lo w t r scl wp sd a (in) sd a (out) t su .wp t hd .wp scl sd a d0 in wr ite data a c k (address (n)) t wc (inter nally controlled) stop condition star t condition write cycle timing rev.0.01, mar.22. 2007, page 6 of 20
HN58X24256AS pin function seri al cl ock (scl) the sc l pi n i s used t o cont rol seri al i nput / out put dat a t i m i ng. the sc l i nput i s used t o posi t i ve edge clock data into eeprom device and ne gative edge clock data out of each device. maximum clock rate is 400 khz. serial input/output data (sda) the sda pi n i s bi di rect i onal for seri al dat a t r ansfer. the sda pi n needs t o be pul l e d up by resi st or as t h at pi n i s open-drai n dri v en st ruct ure. use proper resi st or val u e for your syst em by consi d eri ng v ol , i ol and t h e sda pi n capaci t a nce. except for a st art condi t i on and a st op condi t i on whi c h wi l l be di scussed l a t e r, t h e sda t r ansi t i on needs t o be compl e t e d duri ng t h e sc l l o w peri od. d a ta v a lidity (sda dat a change t i m i ng waveform) scl sd a data change data change note: high-to-low and low-to-high change of sda should be done during the scl low period. rev.0.01, mar.22. 2007, page 7 of 20
HN58X24256AS device address (a0, a1, a2) ei ght devi ces can be wi red for one common dat a bus l i n e as maximum. device address pins are used to distinguish each device a nd device address pins s hould be connected to v cc or v ss . when devi ce address code provi ded from sda pi n mat c hes correspondi ng hard-wi r ed devi ce address pi ns a0 t o a2, t h at one device can be activated. pin connections for a0 to a2 p i n c o n n e c t i o n memory size max connect number a2 a1 a0 note 256k bit 8 v cc /v ss v cc /v ss v cc /v ss note: 1. ?v cc /v ss ? means that device address pin should be connected to v cc or v ss . write protect (wp) when t h e wri t e prot ect pi n (wp) i s hi gh, t h e wri t e prot ect i on feat ure i s enabl e d and operat e s as shown i n th e fo llo w i n g tab l e. wh en th e wp is lo w , w r ite o p e ratio n fo r all memo ry array s are allo w e d . th e read operat i on i s al ways act i v at ed i rresp ective of the wp pin status. write protect area w r ite protect area w p pin status 256k bit v ih full (256k bit) v il normal read/write operation rev.0.01, mar.22. 2007, page 8 of 20
HN58X24256AS functional description start condition a hi gh-t o -l ow t r ansi t i on of t h e sda wi t h t h e sc l hi gh i s needed i n order t o st art read, wri t e operat i on (see st art condi t i on and st op condi t i on). stop condition a l o w-t o -hi gh t r ansi t i on of t h e sda wi t h t h e sc l hi gh i s a st op condi t i on. the st and-by operat i on st art s aft e r a read sequence by a st op condi t i on. in t h e case of wri t e operat i on, a st op condi t i on t e rmi n at es t h e write data inputs and place the device in a internally -timed write cycle to th e memories. after the in tern ally -timed w r ite cy cl e which is specified as t wc , t h e devi ce ent e rs a st andby mode (see wri t e cycl e timin g ) . start condition and stop condition scl sd a (in) stop condition star t condition rev.0.01, mar.22. 2007, page 9 of 20
HN58X24256AS acknowledge all addresses and data words are serially transmitted to and from in 8-bit words. the receiver sends a zero to acknowledge that it has received each word. this happens during nint h clock cycle. the transmitter keeps bus open to receive acknowledgment from the receive r at the ninth clock. in the write operation, eeprom sends a zero to acknowledge after receiving ever y 8-bit words. in the read operation, eeprom sends a zero to acknowledge after receiving the devi ce address word. after sending read data, the eeprom waits acknowledgment by keeping bus open. if the eeprom receives zero as an acknowledge, it sends read data of next address. if the eeprom receives acknowledgment "1" (no acknowledgment) and a fol l o wi ng st op condi t i on, i t st ops t h e read ope rat i on and ent e rs a st and-by mode. if t h e eepr o m receives neither acknowledgment "0" nor a stop c ondition, the eeprom keeps bus open wit hout sending read data. acknowledge timing waveform scl sd a in sd a out 12 8 9 ac kno wledge out rev.0.01, mar.22. 2007, page 10 of 20
HN58X24256AS device addressing the eepr o m devi ce requi res an 8-bi t devi ce address word fol l owi ng a st art condi t i on t o enabl e t h e chi p for a read or a wri t e operat i on. the devi ce address wo rd consi s t s of 4-bi t devi ce code, 3-bi t devi ce address code and 1-bi t read/ w ri t e (r / w ) code. the most si gni fi cant 4-bi t of t h e devi ce address word are used t o di st i ngui sh devi ce t ype and t h i s eepr o m uses ?1010? fi xed code. the devi ce address word i s fol l o wed by t h e 3-bi t devi ce address code i n t h e order of a2, a1, a0. the devi ce address code sel ect s one devi ce out of al l devi ces whi c h are connect ed t o t h e bus. thi s means that the device is selected if the inputted 3- bi t devi ce address code i s equal t o t h e correspondi ng ha rd-wi r ed a2-a0 pi n st at us. the ei ght h bi t of t h e d e v i ce ad d r ess w o rd is th e read /w rite(r/w) b it. a w r ite o p e ratio n is in itiated if th is b i t is lo w an d a read operat i on i s i n i t i at ed i f t h i s bi t i s hi gh. upon a compare of t h e devi ce address word, t h e eepr o m ent e rs t h e read or wri t e operat i on aft e r out put t i ng t h e zero as an acknowl e dge. the eepr o m t u rns t o a st and-by st at e i f t h e devi ce code i s not ?1010? or devi ce addre ss code doesn?t coi n ci de wi t h st at us of t h e correspond hard-wi r ed devi ce address pi ns a0 t o a2. device address word device address word (8-bit) device code (fixed) device address code r/w code * 1 2 5 6 k 1 0 1 0 a 2 a 1 a 0 r/w note: 1. r/w = ? 1? is read and r/w = ?0? is write. rev.0.01, mar.22. 2007, page 11 of 20
HN58X24256AS write operations by te write: a wri t e operat i on requi res an 8-bi t devi ce address word wi t h r / w = ?0?. then t h e eepr o m sends acknowledgment "0" at the ninth clock cycle. af ter these, the 128kbit and 256kbit eeproms receive 2 sequence 8-bit memory address words. upon recei pt of this memory address, the eeprom outputs acknowledgment "0" and receives a following 8-bit write data. after receipt of write data, the eeprom outputs acknowledgment "0". if the eeprom recei ves a stop condition, the eeprom enters an internally-timed write cycle and term inates receipt of scl, sda inputs un til completion of the write cycle. the eepr o m ret u rns t o a st andby mode aft e r compl e t i on of t h e wri t e cycl e. byte write operation de vice address 1st memor y address (n) 2nd memor y address (n) wr ite data (n) 256k 10 10 w a12 a11 a14 a13 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 stop star t ac k ac k ac k r/w * 1 note: 1. don't care bit rev.0.01, mar.22. 2007, page 12 of 20
HN58X24256AS page wri t e: the eepr o m i s capabl e of t h e page wri t e operat i on wh i c h al l o ws any number of byt es up t o 64 byt es t o be written in a single write cycle. the page write is the same sequence as the byte write except for inputting the more write data. the page write is initiated by a start conditi on, device address word, memory address(n) and wri t e dat a (dn) wi t h every ni nt h bi t acknowl e dgment . the eepr o m ent e rs t h e page write operation if the eeprom receives more write data (dn+1) inst ead of receiving a stop condition. the a0 to a5 address bits are automatically incremented upon receiving write data (dn+1). the eeprom can continue to receive write data up to 64 bytes . if the a0 to a5 addre ss bits reaches the last ad d r ess o f th e p a g e , th e a0 to a5 ad d r ess b its w ill ro ll o v e r to th e first ad d r ess o f th e same p a g e an d previous write data will be overwritten. upon receiving a stop condition, the eeprom stops receiving w r ite d a ta an d en ters in tern ally -timed w r ite cy cle. page write operation note: 1. don't care bit de vice address 1st memor y address (n) 2nd memor y address (n) wr ite data (n+m) wr ite data (n) 256k 10 10 w a12 a11 a14 a13 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d5 d4 d3 d2 d1 d0 stop star t ac k ac k ac k ac k ac k r/w * 1 rev.0.01, mar.22. 2007, page 13 of 20
HN58X24256AS acknowl edge pol l i n g: acknowledge polling feature is used to show if the eep rom is in a inte rnally-timed write cycle or not. thi s feat ure i s i n i t i a t e d by t h e st op condi t i on aft e r i nput t i ng wri t e dat a . thi s requi res t h e 8-bi t devi ce address word fol l o wi ng t h e st art condi t i on duri ng a i n t e rnal l y -t i m ed wri t e cycl e. acknowl e dge pol l i ng wi l l operat e when t h e r / w code = ?0?. acknowl e dgment ?1? (no acknowl e dgment ) shows t h e eepr o m i s i n a i n t e rnal l y -t i m ed wri t e cycl e and acknowl e dgment ?0? shows t h at t h e i n t e rnal l y -t i m ed wri t e cycl e has compl e t e d. see wri t e c y cl e pol l i ng usi ng ac k. write c y cle po lling u s ing a c k send wr ite command send stop condition to initiate wr ite cycle send star t condition send de vice address w ord with r/w = 0 send memor y address send star t condition send stop condition send stop condition proceed r andom address read oper ation proceed wr ite oper ation ne xt oper ation is addressing the memor y ye s ye s no no ac k retur ned rev.0.01, mar.22. 2007, page 14 of 20
HN58X24256AS read operati on there are t h ree read operat i ons: current address r ead, random read, and sequent i a l read. r ead operat i ons are initiated the same way as write opera tions with the exception of r/w = ?1?. current address read: the internal address counter mainta ins the last address accessed during th e last read or write operation, with incremented by one. current address read accesses the address kept by the in ternal address counter. after receiving a start condition and the device address word (r/w is ?1?), the eeprom outputs the 8-bit current address dat a from t h e most si gni fi cant bi t fol l o wi ng acknowl e dgment ?0?. if t h e eepr o m receives acknowledgment ?1? (no acknowledgment) a nd a following stop condition, the eeprom stops the read operation and is turned to a standby state. in case the eeprom has accessed the last address of t h e l a st page at previ ous read operat i on, t h e current a ddress wi l l rol l over and ret u rns t o zero address. in case the eeprom has accessed the last address of the page at previous write opera tion, the current address wi l l rol l over wi t h i n page addressi ng and ret u rns t o t h e fi rst address i n t h e same page. the current address i s val i d whi l e power i s on. the current address aft e r power on wi l l be i ndefi ni t e . the random read operat i on descri bed bel o w i s necessary t o defi ne t h e memory address. current address read operation 256k de vice address read data (n+1) star t stop 10 10 r d7 d6 d5 d4 d3 d2 d1 d0 ac k no a c k r/w rev.0.01, mar.22. 2007, page 15 of 20
HN58X24256AS random read: thi s i s a read operat i on wi t h defi ned read address. a random read requi res a dummy wri t e t o set read address. the eeprom receives a start condition, de vice address word (r/w=0) and memory address 2 8-bit sequentially. the eeprom outputs acknowledgment ?0? after receiving memory address then enters a current address read with receivi ng a start condition. the eeprom output s the read data of the address which was defined in the dummy write opera tion. after receiving acknowledgment ?1?(no acknowledgment) and a following stop condition, th e eeprom stops the random read operation and ret u rns t o a st andby st at e. random read operati on @@ @ notes: 1. don't care bit 2. 2nd de vice address code (#) should be same as 1st (@). de vice address de vice address 1st memor y address (n) 2nd memor y address (n) read data (n) 256k 10 10 ## # 10 10 r w a12 a11 a14 a13 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 stop star t star t ac k ac k no a c k ac k r/w ac k r/w * 1 dumm y wr ite currect address read rev.0.01, mar.22. 2007, page 16 of 20
HN58X24256AS sequential read: sequential reads are initiated by either a current addr ess read or a random read. if the eeprom receives acknowl e dgment ?0? aft e r 8-bi t read dat a , t h e read addre ss i s i n crement e d and t h e next 8-bi t read dat a are coming out. this operation can be continued as long as the eeprom receives acknowledgment ?0?. the address will roll over and returns addr ess zero if it reaches the last addre ss of the last page. the sequential read can be continued after roll over. the seque ntial read is terminated if the eeprom receives acknowl e dgment ?1? (no acknowl e dgment ) and a fol l o wi ng st op condi t i on. sequential read operation de vice address read data (n+m) read data (n) read data (n+1) read data (n+2) 256k 10 10 r d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 stop star t ac k ac k no a c k ac k r/w ac k rev.0.01, mar.22. 2007, page 17 of 20
HN58X24256AS notes data protecti o n at v cc on/off when v cc i s t u rned on or off, noi se on t h e sc l and sda i nput s generat e d by ext e rnal ci rcui t s (c pu, et c) may act as a t r i gger and t u rn t h e eepr o m t o uni nt ent i onal program mode. to prevent t h i s uni nt ent i onal programmi ng, t h i s eepr o m has a power on reset funct i on. b e careful of t h e not i ces descri bed bel o w i n order for t h e power on reset funct i on t o operat e correct l y . ? sc l and sda shoul d be fi xed t o v cc or v ss duri ng v cc on/ off. low t o hi gh or hi gh t o l o w t r ansi t i on duri ng v cc on/ off may cause t h e t r i gger for t h e uni nt ent i onal programmi ng. ? v cc should be turned off after the eep rom is placed in a standby state. ? v cc shoul d be t u rned on from t h e ground l e vel ( v ss ) in order for the eeprom not to enter the uni nt ent i onal programmi ng mode. ? v cc t u rn on speed shoul d be l onger t h an 10 s. noise suppression time thi s eepr o m have a noi se suppressi on funct i on at sc l and sda i nput s, t h at cut noi se of wi dt h l e ss t h an 50 ns. b e careful not t o al l o w noi se of wi dt h more t h an 50 ns. rev.0.01, mar.22. 2007, page 18 of 20
HN58X24256AS package dimensions HN58X24256ASfpi (pr sp0008df-b / previ ous c ode: fp-8db v ) a l e c 1 b 1 d e a 2 b p c x y h e z l 1 4.89 1.06 0.25 0 8 6.02 0.15 0.20 0.25 0.45 0.102 0.14 0.254 3.90 0.406 0.60 0.889 1.73 reference symbol dimension in millimeters min nom max 5.15 a 1 0.35 0.40 6.20 5.84 1.27 0.10 0.69 index mark e 1 y xm p * 3 * 2 * 1 f 4 85 d e h a z b p terminal cross section ( ni/pd/au plating ) b c detail f 1 1 l l a note) 1. dimensions" * 1 (nom)"and" * 2" do not include mold flash. 2. dimension" * 3"does not include trim offset. e p-sop8-3.9x4.89-1.27 0.08g mass[typ.] fp-8dbv prsp0008df-b renesas code jeita package code previous code rev.0.01, mar.22. 2007, page 19 of 20
HN58X24256AS rev.0.01, mar.22. 2007, page 20 of 20 HN58X24256ASt i (ptsp0014ja-c / previ ous c ode: ttp-14db v ) y xm p * 3 7 1 index mark e * 2 14 8 * 1 f a d e h z b 1 1 detail f l l a p terminal cross section ( ni/pd/au plating ) b c 0.83 0.10 0.65 6.20 6.60 0.20 0.15 a 1 5.30 max nom min dimension in millimeters symbol reference 1.10 0.60 0.50 0.40 4.40 0.10 0.07 0.03 0.25 0.20 0.15 0.10 6.40 8 0 0.13 1.00 5.00 l 1 z h e y x c b p a 2 e d b 1 c 1 e l a note) 1. dimensions" * 1 (nom)"and" * 2" do not include mold flash. 2. dimension" * 3"does not include trim offset. e p-tssop14-4.4x5-0.65 0.05g mass[typ.] ttp-14dbv ptsp0014ja-c renesas code jeita package code previous code
revision history HN58X24256AS data sheet contents of modification r e v . d a t e p a g e d e s c r i p t i o n 0.01 mar. 22, 2007 ? i n i t i a l i s s u e
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(http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the t otal system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding th e suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this do cument or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not desi gned, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of h uman injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion co ntrol, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a r enesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to us e renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, dir ectors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas sha ll have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristic s such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the poss ibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, sinc e the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from r enesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renes as semiconductor products, or if you have any other inquiries. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices ? 200 7. re nesas technology corp ., all rights reser v ed. printed in ja pan. colophon .7.0

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